?digitally controlled electronic potentiometer ?8-bit digital-to-analog converter (dac) ?independent reference inputs ?differential non-linearity - ?.5lsb max ?integral non-linearity - ?lsb max ?v out value in eeprom for power-on recall ?equivalent to 256-step potentiometer ?unity gain op amp drives up to 1ma ?simple trimming adjustment ?up/down counter style operation ?low noise operation make-before-break contact for ?lickless transitions between dac steps ?operation from +2.7v to +5.5v supply ?low power, 1mw max at +5v ?no mechanical wearout problem ?1,000,000 stores (typical) ?100 year data retention ?fool-proof, set-and-forget calibrations the new telephone: 800.874.1874 fax: 800.223.5138 12055 rojas drive ? suite k ? el paso, texas usa 79936 ? www.clarostat.com series cc9318 new the clarochip cc9318 digital trimming potentiometer is an 8-bit non- volatile dac designed to replace mechanical trimmers. it includes a unity-gain amplifier to buffer the dac output and enables v out to swing from rail to rail. the digital trimming potentiometer operates over a supply voltage range of 2.7v to 5.5v. the simple up/down counter input provides an ideal interface for automatic test equipment to dither and monitor the v out voltage. this interface allows for quick and consistent calibration of even the most sophisticated systems. the cc9318 is a pin-compatible performance upgrade for other industry nonvolatile potentiometers. the adjustable clarochip cc9318 offers double the reso- lution of these devices and provides clickless?transitions of v out . - + counter & write control inc up/dn cs gnd v h v out v dd 8-bit e 2 prom v l 8-bit data register 8-bit dac 2016 ill2 1 amp functional block diagram .............................. claro chip nonvolatile digital trimming potentiometer features .........................................
symbol inc up/dn v h gnd v out v l cs v dd description increment input, high to low edge trigger up/down input controlling relative vout movement v+ reference input analog and digital ground trimmed voltage output v- reference input active low chip select input supply voltage (2.7v to 5.5v) inc up/dn v h gnd 1 2 3 4 8 7 6 5 v dd cs v l v out analog section the cc9318 is an 8-bit, voltage output digital-to-analog converter (dac). the dac consists of a resistor network that converts an 8-bit value into equivalent analog output voltages in proportion to the applied reference voltage. reference inputs the voltage differential between the v l and v h inputs sets the full- scale output voltage range. v l must be equal to or greater than ground (i.e. a positive voltage). v h must be greater than v l and less than or equal to v dd . see table on page 3 for guaranteed operating limits. output buffer amplifier the voltage output is a precision unity-gain follower that can slew up to 1v/?. digital interface the interface is designed to emulate a simple up/down counter, but instead of a parallel count output, a ratiometric voltage output is provided. chip select (cs) is an active low input. whenever cs is high the cc9318 is in standby mode and consumes the least power. this mode is equivalent to a potentiometer that is adjusted to the required setting. when cs is low the cc9318 will recognize transi- tions on the inc input and will move the v out either toward the v h reference or toward the v l reference depending upon the state of the up/dn input. the host may exit an adjustment routine in two ways: deselecting the cc9318 while inc is low will not perform a store operation (a subsequent power cycle will recall the original data); deselecting the cc9318 while inc is high will store the current v out setting into nonvolatile memory. increment (inc) is an edge triggered input. whenever cs is low and a high to low transition occurs on the inc input, the v out voltage will either move toward v h or v l depending upon the state of the up/dn input. up/down (up/dn) is an input that will determine the v out move- ment relative to v h and v l . when cs is low, up/dn is high and there is a high to low transition on inc, the v out voltage will move (1/256 th x v h -v l ) toward v h. when cs and up/dn are low, and there is a high to low transition on inc, the v out will move (1/256 th x v h -v l ) toward v l . power?p/power?own conditions on power?p the cc9318 loads the value of eeprom memory into the wiper position register. the value in the register is changed using the cs, inc, and up/dn pins. the new data in the register will be lost at power-down unless cs was brought high, with inc high, to initiate a store operation after the last increment or decre- ment. on the next device power?p, the value of eeprom memory will be loaded into the wiper position register. during power-up the cc9318 is write-protected in two ways: 1) a power-on reset, that trips at approximately 2.5v, holds cs and inc high internally. 2) resistor pull-ups on all logic inputs prevent data change if the inputs are floating. data retention the cc9318 is guaranteed to perform at least 1,000,000 writes to eeprom before a wear?ut condition can occur. after eeprom wearout, the cc9318 continues to function as a volatile digital potentiometer. the wiper position can be changed during powered conditions using the digital interface. however, on power?p the wiper position will be indeterminate. on shipment from the factory, clarostat does not specify any eep- rom memory value. the value must be set by the customer as needed. absolute maximum ratings* temperature under bias -55? to +125? storage temperature -65? to +150? voltage on pins with reference to gnd: analog inputs -0.5v to v dd +.5v digital inputs -0.5v to v dd +.5v analog outputs -0.5v to v dd +.5v digital outputs -0.5v to v dd +.5v lead solder temperature (10 secs) 300? *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other condi- tions outside those listed in the operation sections of this specifica- tion is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. page 2
symbol parameter conditions min. typ. max. units accuracy inl integral non-linearity i load = 100? - 0.5 ? lsb dnl differential non-linearity i load = 100? - 0.1 ?.5 lsb guaranteed but not tested references v h v refh input voltage v refl -v dd v v l v refl input voltage gnd - v refh v r in v refh to vrefl resistance - 38k - ? tcr in temperature coefficient v refh to v refl - 600 - ppm/? of r in analog g efs full-scale gain error data = ff - - ? lsb output v out zs zero-scale output voltage data = 00 0 20 mv tcv out v out temperature v dd = +5, i load = 50?, coefficient v refh = +5v, v refl = 0v - - 50 ?/? guaranteed but not tested i l amplifier output load current -200 +1000 ? r out amplifier output resistance i l = 100? v dd = +5v - 10 ? v dd = +3v - 20 ? psrr power supply rejection i load = 10? - - 1 lsb/v e n amplifier output noise f = 1khz, v dd = +5v - 90 - nv/ hz thd total harmonic distortion v in = 1v rms, f = 1khz - 0.08 - % bw bandwidth - 3db v in = 100mv rms - 300 - khz dac dc electrical characteristics v dd = +2.7v to +5.5v, v refh = v dd , v refl = 0v, t a = -40? to +85?, unless specified otherwise symbol parameter min max unit test method v zap esd susceptibility 2000 v ms-883, tm 3015 i lth latch-up 100 ma jedec standard 17 t dr data retention 100 years ms-883, tm 1008 n end endurance 1,000,000 stores ms-883, tm 1033 symbol parameter conditions min max units i dd supply current cs = v il to v ih 1.2 ma during store, note 1 w/inc hi i sb supply standby current cs = v ih 200 ? i ih input leakage current v in = v dd 10 ? i il input leakage current, note 2 v in = 0v -25 ? v ih high level input voltage 2 v dd v v il low level input voltage v dd 4.5v 0 0.8 v notes: 1. i dd is the supply current drawn while the eeprom is being updated. i dd does not include the current that flows through the reference resistor chain. 2. cs, up/dn and inc have internal pull-up resistors of approximately 200k ? . when the input is pulled to ground the resulting output current will be v dd /200k ? . dc electrical characteristics v dd = +2.7v to +5.5v, v h = v dd , v l = 0v, t a = -40? to +85?, unless otherwise specified reliability characteristics (over recommended operating conditions unless otherwise specified) page 3 condition min max temperature -40? +85? v dd +2.7v 5.5v recommended operating conditions
inc cs up/dn operation hi to lo l h v out toward v h hi to lo l l v out toward v l h lo to hi x store setting l lo to hi x maintain setting, no store x h x standby, note 1 notes: 1. the standby or operating current will be lowest with inc and up/dn pins at h due to weak internal pull-ups that draw current when connected lo. operational truth table ac timing characteristics vdd = +4.5v to +5.5v symbol parameter min max units t clil cs to inc setup 100 ns t ihdc inc high to up/dn change 100 ns t dcil up/dn to inc setup 100 ns t il inc low period 200 ns t ih inc high period 200 ns t ihch inc inactive to cs inactive 100 ns t wp write cycle time 5 ms t ilvout inc to v out delay 5 ? t clil t il t ihdc t ih t ihdhld t ihch t wp t ilvout cs inc up/dn v out ac timing diagram page 4 .228 (5.80) .244 (6.20) .016 (.40) .035 (.90) .020 (.50) .010 (.25) x45 .0192 (.49) .0138 (.35) .061 (1.75) .053 (1.35) .0098 (.25) .004 (.127) .05 (1.27) typ. .275 (6.99) typ. .030 (.762) typ. 8 places .050 (1.27) typ. .050 (1.270) typ. 8 places .157 (4.00) .150 (3.80) .196 (5.00) 1 .189 (4.80) footprint 8pn jedec soic 8 pin soic (type s) package jedec (150 mil body width) .300 (7.620) 5 -7 typ. (4 plcs) .350 (8.89) .009 .002 (.229 .051) 0 -15 .015 (.381) min. .130 (3.302) .100 (2.54) typ. .018 (.457) typ. .060 .005 (1.524) .127 typ. .130 (3.302) seating plane .070 (1.778) .0375 (0.952) .375 (9.525) pin 1 indicator .250 (6.350) 8 pin dip (type p) package jedec (250 mil body width) package s = 8 pin soic p = 8 pin dip base part number cc9318 s how to order
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